1. Field of the Invention
The present invention relates generally to processes for semiconductor manufacture and more particularly to semiconductor pattern overlay.
2. Description of Related Art
Lithographic processing is increasingly requiring ever tighter layer-to-layer overlay tolerances to meet device performance requirements. Overlay registration on critical layers can directly impact device performance, yield and repeatability. Increasing device densities, decreasing device feature sizes and greater overall device size conspire to make pattern overlay one of the most important performance issues during the semiconductor manufacturing process. The ability to accurately determine correctable and uncorrectable pattern placement error depends on fundamental techniques and algorithms used to calculate lens distortion, stage error, and reticle error.
Overlay registration generally refers to translational error that exists between features exposed layer to layer in a vertical fabrication process of semiconductor devices on silicon wafers. Other names for overlay registration include, registration error and pattern placement error. A typical microelectronic device or circuit may consist of 20-30 levels or pattern layers. The placement of patterned features on other levels must match the placement of corresponding features on other levels, commonly referred to as overlap, within an accuracy which is some fraction of the minimum feature size or critical dimension (CD).
Overlay error is typically, although not exclusively, measured with an optical overlay metrology tool. See Semiconductor Pattern Overlay, N. Sullivan, SPIE Vol. 3051, 426:432, 1997; Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects, A. Starikov et al., Optical Engineering, 1298:1309, 1992; KLA 5105 Overlay Brochure, KLA-Tencor; KLA 5200 Overlay Brochure, KLA Tencor; Quaestor Q7 Brochures, Bio-rad Semiconductor Systems. Lithographers have crafted a variety of analysis techniques that attempt to separate out systematic process induced overlay error from random process induced error using a variety of statistical methods. See A Computer Aided Engineering Workstation for Registration Control, E. McFadden, C. Ausschnitt, SPIE Vol. 1087, 255:266, 1989; A xe2x80x9cGolden Standardxe2x80x9d Wafer Design for Optical Stepper Characterization, K. Kenp, C. King, W. W, C. Stager, SPIE Vol. 1464, 260:266, 1991; Matching Performance for Multiple Wafer Steppers using an Advanced Metrology Procedure, M. Van den Brink et al., SPIE Vol. 921, 180:197, 1988; Characterizing Overlay Registration of Concentric 5xc3x97 and 1xc3x97 Stepper Exposure Fields Using Interfield Data, F. Goodwin, J. Pellegrini, SPIE Vol. 3050, 407:417, 1997; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, J. Pellegrini, SPIE Vol. 3677, 72:82, 36220.
The importance of overlay error and its impact to yield can be found elsewhere. See Measuring Fab Overlay Programs, R. Martin, X. Chen, I. Goldberger, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 64:71, March 1999; A New Approach to Correlating Overlay and Yield, M. Preil, J. McCormack, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, 208:216, March 1999. Lithographers have created statistical computer algorithms (for example, Klass II (See Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment, A. Yost et al., SPIE Vol. 1087, 233:244, 1989) and Monolith (See A Computer Aided Engineering Workstation for Registration Control, supra)) that attempt to separate out correctable sources of pattern placement error from non-correctable sources of error. See Analysis of overlay distortion patterns, J. Armitage, J. Kirk, SPIE Vol. 921, 207:221, 1988; Method to Budget and Optimize Total Device Overlay, C. Progler et al., SPIE Vol. 3679, 193:207, 1999; and System and Method for Optimizing the Grid and Intrafield Registration of Wafer Patterns, J. Pellegrini, U.S. Pat. No. 5,444,538 issued Aug. 22, 1995. Overall theoretical reviews of overlay modeling can be found in See Semiconductor Pattern Overlay, supra; Machine Models and Registration, T. Zavecz, SPIE Critical Reviews Vol. CR52, 134:159.
Typically, most overlay measurements are made on silicon product wafers after each lithographic process, prior to final etch. Product wafers cannot be etched until the alignment attributes or overlay target patterns are properly aligned to the underlying overlay target patterns. Examples of overlay targets are described in Overlay Alignment Measurement of Wafers, N. Bareket, U.S. Pat. No. 6,079,256 issued Jun. 27, 2000 (at FIG. 1b), Matching Management of Multiple Wafer Steppers Using a Stable standard and a Matching Simulator, M. Van den Brink et al., SPIE Vol. 1087, 218:232, 1989; Automated Electrical Measurements of Registration Errors in Step and Repeat Optical Lithography Systems, T. Hasan et al., IEEE Transactions on Electron Devices, Vol. ED-27, No. 12, 2304:2312, December 1980; Method of Measuring Bias and Edge Overlay Error for Sub 0.5 Micron Ground Rules, C. Ausschnitt et al., U.S. Pat. No. 5,757,507 issued May 26, 1998; Capacitor Circuit Structure for Determining Overlay Error, K. Tzeng et al., U.S. Pat. No. 6,143,621 issued Nov. 7, 2000.
Generally, manufacturing facilities rely heavily on exposure tool alignment, wafer stage matching and calibration procedures (See Stepper Matching for Optimum Line Performance, T. Dooly, Y. Yang, SPIE Vol. 3051, 426:432, 1997; Matching Management of Multiple Wafer Steppers Using a Stable standard and a Matching Simulator, supra), Matching Performance for Multiple Wafer Steppers using and Advanced Metrology Procedure, supra) to help insure that the stepper or scanner tools are aligning properly; inaccurate overlay modeling algorithms can corrupt the exposure tool calibration procedures and degrade the alignment accuracy of the exposure tool system. See Characterizing Overlay Registration of Concentric 5xc3x97 and 1xc3x97 Stepper Exposure Fields Using Interfield Data, supra.
Over the past 30 years the microelectronics industry has experienced dramatic, and rapid decreases in critical dimension in part due to improving lithographic imaging systems. See A New Lens for Submicron Lithography and its Consequences for Wafer Stepper Design, J. Biesterbos et al., SPIE Vol. 633, Optical Microlithography V, 34:43, 1986; New 0.54 Aperture I-Line Wafer Stepper with Field by Field Leveling Combined with Global Alignment, M. Van den Brink, B. Katz, S. Wittekoek, SPIE Vol. 1463, 709:724; Step and Scan and Step and Repeat, a Technology Comparison, M. Van den Brink et al., SPIE Vol. 2726, 734:753; 0.7 NA DUV Step and Scan System for 150 nm Imaging with Improved Overlay, J. V. School, SPIE Vol. 3679, 448:463, 1999. Today, these photolithographic exposure tools or machines are pushed to their performance limits. As the critical dimensions of semiconductor devices approach 50 nm the overlay error requirements will soon approach atomic dimensions. See Life Beyond Mix-and-Match: Controlling Sub-0.18 Micron Overlay Errors, T. Zavecz, Semiconductor International, July 2000. To meet the needs of next generation device specifications new overlay methodologies need to be developed. In particular, overlay methodologies that can accurately separate out systematic and random effects and break them into assignable causes may greatly improve device process yields. See A New Approach to Correlating Overlay and Yield, supra; Expanding Capabilities in Existing Fabs with Lithography Tool-Matching, F. Goodwin et al., Solid State Technology, 97:106, June 2000; Super Sparse Overlay Sampling Plans: An Evaluation of Methods and Algorithms for Optimizing Overlay Quality Control and Metrology Tool Throughput, supra; Lens Matching and Distortion Testing in a Multi-Stepper, Sub-Micron Environment, supra.
New xe2x80x9cmix and matchxe2x80x9d technologies that can quickly and accurately reduce the registration error through better calibration and cross referencing procedures are desirable. See Mix-and-Match: A Necessary Choice, R. DeJule, Semiconductor International, 66:76, February 2000.
In accordance with the invention, a process for manufacturing, using, and maintaining a calibrated registration reference wafer for use in semiconductor manufacturing facilities is described. A reference reticle consisting of, for example, a 2-dimensional array of standard alignment attributes is exposed in an interlocking field pattern onto a photoresist coated semiconductor wafer using a photolithographic exposure tool. Following the lithographic development process, the resist patterned wafer is physically etched using standard techniques, thereby creating a permanent record of the alignment attribute exposure pattern. Along the interlocking rows and columns of the resulting wafer, the permanently recorded alignment attributes are measured for placement error using a conventional overlay metrology tool. The resulting overlay error data may be used, for example, in a software program, to generate a unique reference wafer calibration file that contains the positions of all the reference marks (alignment attributes) forming an uninterrupted, regular array across the wafer as well as the wafer alignment marks. The positions of these alignment attributes on the reference wafer can be determined very accurately, except for the possibility of arbitrary translation, rotation, asymmetric scaling and non-orthogonal positional offset errors.
The reference wafer and its associated calibration file can be used to determine the wafer stage registration performance for any photolithographic exposure tool. The accuracy and the precision of the calculated registration error are controlled, in large part, by the number of alignment attributes and overlay measurements. In addition, the process can be quickly repeated resulting in multiple reference wafers. Because of the ease of manufacture of this article, each photolithographic exposure tool in a semiconductor factory can have its own unique reference wafer for routine monitoring. Furthermore, the method of calculating the positional coordinates of the alignment attributes for the preferred reference wafer are more accurate and precise as compared to other techniques. The reference wafer, and its associated calibration file, may then be used as a calibrated ruler for measuring registration error induced by any photolithographic exposure tool, independently from a reference machine. Because a conventional overlay metrology tool is used for local measurements to extract global wafer stage and lens distortion, the above described process can be easily implemented in a semiconductor fabrication facility. Additional applications of the resulting calibrated reference wafers include; improved lithographic simulation using conventional optical modeling software, advanced process control in the form of feedback loops that automatically adjust the projection lens, reticle stage, and wafer stage for optimum registration performance.
The reference wafer, or archive wafer, and its associated calibration file functions as a xe2x80x9crulerxe2x80x9d and it can be used like a traditional xe2x80x9cgolden waferxe2x80x9d in the sense that an exposure of the reference marks 3302 illustrated in FIG. 33, by any lithographic projection tool. For example, a set of complementary marks like the outer box 2702, illustrated in FIGS. 27 and 28 or the outer box 1302 and inner box 1304 marks illustrated in FIGS. 13A and 13B, result in a box-in-box structure or complete alignment attribute that can be measured with a conventional overlay metrology tool. Using the measurements from the overlay metrology tool and subtracting the corrections provided by the reference wafer calibration file from the overlay measurements, the combination of the intra-field and the inter-field errors of a machine can be directly interpreted. By accounting for stage distortion and yaw effects during the determination of the calibration, the inherent machine-to-machine reference errors of the prior art golden wafer method are effectively eliminated. See A xe2x80x9cGolden Standardxe2x80x9d Wafer Design for Optical Stepper Characterization, supra; Matching Management of Multiple Wafer Steppers Using a Stable standard and a Matching Simulator, supra.
Improvement in the measurement accuracy reduces the need for cross calibration between different photolithographic exposure tool sets and allows direct interpretation, after calibration file correction, of the results of a set of overlay measurements using the reference wafer. Errors in the overlay measurements due to the exposure of the present machine and not as due to systematic or random errors associated with the machine on which the reference wafer was manufactured. The technique described above can adjust the accuracy by adjusting the number of alignment attributes or overlay measurements.
A technique in accordance with the present invention includes providing a reticle, exposing a reference wafer in such a way as to create a unique pattern of overlapped interlocking alignment attributes, etching the reference wafer, measuring the interlocked alignment attributes, and finally creating a reference wafer calibration file that permanently records the positional coordinates of the alignment attributes. Additionally, other embodiments may allow production of a robust set of reference wafers for manufacturing facilities that use scanners in addition to steppers. For this case, we minimize the non-repeatable source of intra-field error associated with the moving scanner stage during the exposure of the reference wafer by using a special reticle and multiple exposures. By utilizing a high precision overlay metrology tool for local measurements and extracting a global set of calibrated positional measurement, the metrology error multiplier can be kept near unity.
FIG. 6 is a flow chart illustrating an embodiment for creating a reference wafer. In block 602, a reference reticle, for example the reticle illustrated in FIGS. 13A, 13B, 13C, 14 containing an array of alignment attributes 1302, 1304, 1306 and wafer alignment marks 1308, is loaded into an exposure tools"" reticle management system 1002, as illustrated in FIG. 10, and aligned. Wafers possibly laser or otherwise scribed with unique wafer identification codes and possibly coated with various thin films are provided. Examples of such thin films on silicon wafers are silicon nitride, silicon dioxide, amorphous silicon, or polysilicon.
Flow continues to block 604 where the wafer is then coated with photoresist and loaded into a projection imaging tool or machine and exposed, in block 606, in an overlapping interlocking pattern. Examples of overlapping interlocking patterns are illustrated in FIGS. 12 and 16A. The projection imaging tool may include contact or proximity printers, steppers, scanners, direct write, e-beam, x-ray, SCALPEL, IPL, or EUV machines. See Direct-Referencing Automatic Two-Points Reticle-to-Wafer Alignment Using a Projection Column Servo System, M. Van den Brink, H. Linders, S. Wittekoek, SPIE Vol. 633, Optical Microlithography V, 60:71, 1986; New 0.54 Aperture I-Line Wafer Stepper with Field by Field Leveling Combined with Global Alignment, supra; Refs 4861146, Micrascan(trademark) III Performance of a Third Generation, Catadioptric Step and Scan Lithographic Tool, D. Cote et al., SPIE Vol. 3051, 806:816, 1997; Step and Scan Exposure System for 0.15 Micron and 0.13 Micron Technology Node, J. Mulkens et al., SPIE Conference on Optical Microlithography XII, 506:521, March 1999; 0.7 NA DUV Step and Scan System for 150 nm Imaging with Improved Overlay, supra; Optical Lithographyxe2x80x94Thirty Years and Three Orders of Magnitude, J. Bruning, SPIE Vol. 3051, 14:27, 1997; Large Area Fine Line Patterning by Scanning Projection Lithography, H. Muller et al., MCM 1994 Proceedings, 100:104; Large-Area, High-Throughput, High-Resolution Projection Imaging System, K. Jain, U.S. Pat. No. 5,285,236 issued Feb. 8, 1994; Development of XUV Projection Lithography at 60-80 nm, B. Newnam et al., SPIE Vol. 1671, 419:436, 1992; Mix-and-Match: A Necessary Choice, supra. In the examples illustrated in FIGS. 12 and 16A, each exposure field is separated from the previous exposure by a desired distance such that neighboring fields have their corresponding interlocking rows or columns overlapped. See Mix-and-Match: A Necessary Choice, supra. This partially overlapping exposure technique is shown in FIGS. 12 and 16A. Following the exposures of the interlocking array, the wafer alignment marks and their corresponding interlocking rows and columns are exposed as separate fields but interlock into the previous exposure set.
Flow then continues to block 608 where, after the final exposure the wafer is removed from the machine and sent through the final few resist development steps. Next, the wafers are etched and stripped of photoresist and possibly overcoated with another layer. This leaves the alignment attributes and wafer alignment marks permanently recorded on the wafer surfaces. Flow then continues to block 610 where the resulting alignment attributes along the interlocking rows and columns are measured for registration, placement or overlay error using an overlay metrology tool such as a KLA-Tencor model 5200. See KLA 5200 Overlay Brochure, supra; KLA 5105 Overlay Brochure, supra; Quaestor Q7 Brochures, supra; Process for Measuring Overlay Misregistration During Semiconductor Wafer Fabrication, I. Mazor et al., U.S. Pat. No. 5,438,413 issued Aug. 1, 1995; Overlay Alignment Measurement of Wafers, supra. FIG. 9 is a schematic illustrating common causes of overlay or placement error for inter-field and intra-field.
Next, in block 612, the intra-field distortion of the projection imaging tool used to create the reference wafer is provided. Flow continues to block 614 when the resulting data set is entered into a computer algorithm where a special calibration file containing the positional coordinates for each alignment attribute is constructed for the reference wafer. The final articles as created by the present invention consist of a reference wafer containing reference marks on a periodic array interrupted only by wafer alignment marks as illustrated in FIG. 33, and a unique calibration file that lists the location of each reference and wafer alignment mark on the wafer as illustrated in FIG. 34. The process described above can be repeated multiple times resulting in numerous individual reference wafers. Once a calibration file is on record and the positions of each alignment attribute is known, the wafer can be used as a two dimensional (2-D) rigid ruler to measure the registration error associated with a given projection imaging toolxe2x80x94similar to the prior art golden wafer techniques. See A xe2x80x9cGolden Standardxe2x80x9d Wafer Design for Optical Stepper Characterization, supra. However, the preferred embodiment allows for the direct measurement of the overlay error unique to the machine being testedxe2x80x94without reference to another machine either directly or indirectly.